MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 268

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

SECTION 8
8.1 E X C E P T I O N P R O C E S S I N G
MOTOROLA
the handler routine itself. An introduction to exception processing, as one of
the processing states of the MC68030 processor, was given in SECTION 4
from an exception and bus fault recovery. This section also describes the
formats of the exception stack frames. For details of MMU-related exceptions,
tocol violation and coprocessor-related exceptions, refer to SECTION 10
COPROCESSOR INTERFACE DESCRIPTION. Also, for more detail on excep-
tions defined for floating-point coprocessors, refer to the user's manual for
the MC68881/MC68882.
this section. Nonetheless, all addresses and offsets from the stack pointer
The first step of exception processing involves the status register. The pro-
cessor makes an internal copy of the status register. Then the processor sets
the S bit, changing to the supervisor privilege level. Next, the processor
the reset and interrupt exceptions, the processor also updates the interrupt
ception. For interrupts, the processor performs an interrupt acknowledge
cycle (a read from the CPU address space type $F; see Figures 7-45 and
7-46) to obtain the vector number. For coprocessor-detected exceptions, the
vector number is included in the coprocessor exception primitive response.
Exception processing is defined as the activities performed by the processor
in preparing to execute a handler routine for any condition that causes an
exception. In particular, exception processing does not include execution of
PROCESSING LEVELS. This section describes exception processing in detail,
describing the processing for each type of exception. It describes the return
refer to SECTION 9 MEMORY MANAGEMENT UNIT. For more detail on pro-
Exception processing occurs in four functional steps. However, all individual
bus cycles associated with exception processing (vector acquisition, stacking,
etc.) are not guaranteed to occur in the order in which they are described in
are guaranteed to be as described.
inhibits tracing of the exception handler by clearing the T1 and TO bits. For
priority mask.
In the second step, the processor determines the vector number of the ex-
EXCEPTION PROCESSING
MC68030 USER'S MANUAL
S E Q U E N C E
8-1
8