MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 197

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-36
State 3
State 4
State 5
State 1
State 2
to place its information on the data bus, and drives CIIN if appropriate.
Any or all of the bytes (D24-D31, D16-D23, D8-D15, and D0-D7) are se-
As long as at least one of the DSACKx signals is recognized by the end of
the asynchronous input setup and hold times around the end of $2. If wait
The processor samples CIIN at the beginning of state 4 ($4). Since CIIN is
the appropriate synchronous input setup and hold times on every rising
The processor negates AS, DS, and DBEN during state 5 ($5). It holds the
The external device keeps its data and DSACKx signals asserted until it
cycle.
the address on the address bus is valid. The processor also asserts DS also
during $1.
lected by SIZ0-SIZ1 and A0-AI. Concurrently, the selected device asserts
DSACKx.
$2 (meeting the asynchronous input setup time requirement), data is latched
on the next falling edge of the clock, and the cycle terminates. If DSACKx
is not recognized by the start of state 3 ($3), the processor inserts wait
states instead of proceeding to states 4 and 5. To ensure that wait states
are inserted, both DSACK0 and DSACK1 must remain negated throughout
states are added, the processor continues to sample the DSACKx signals
on the falling edges of the clock until one is recognized.
defined as a synchronous input, whether asserted or negated, it must meet
edge of the clock while AS is asserted. At the end of $4, the processor
latches the incoming data.
address valid during $5 to provide address hold time for memory systems.
detects the negation of AS or DS (whichever it detects first). The device
period after sensing the negation of AS or DS. DSACKx signals that remain
asserted beyond this limit may be prematurely detected for the next bus
One-half clock later in state 1 ($1), the processor asserts AS indicating that
during $1. In addition, the ECS (and OCS, if asserted) signal is negated
During state 2 ($2), the processor asserts DBEN to enable external data
buffers. The selected device uses R/W, SIZ0-SIZ1, A0-A1, CLOUT, and DS
R/W, SIZ0-SIZ1, and FC0-FC2 also remain valid throughout $5.
must remove its data and negate DSACKx within approximately one clock
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