MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 344

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
9.5.5 P r o t e c t i o n
(L]MIT CHECK NOT REQUIRED)f
These signals identify accesses to the user program space, the user data
function code signals can be used for protection mechanisms by setting the
function code lookup (FCL) bit in the translation control (TC) register.
The MC68030 MMU provides the capability for separate translation trees for
The translation table trees contain both mapping and protection information.
to programs operating at the supervisor privilege level.
are operating on a cycle-by-cycle basis by means of the function code signals.
space, the supervisor program space, and the supervisor data space. The
supervisor and user spaces to be used. When the supervisor root pointer
enable bit (SRE) in the TC register is set, the root pointer register for the
supervisor space translation tree is selected for supervisor program or data
accesses.
Each table and page descriptor includes a write-protect (WP) bit, which can
be set to provide write protection at any level. Each long-format table and
page descriptor also contains a supervisor-only (S) bit, which can limit access
M68000 Family processors provide an indication of the context in which they
RETURN
FCL =
I L I M , T .EOK NOT REOUI R EOI F
Figure 9-28. Limit Check Procedure Flowchart
)
1 ~
MC68030 USER'S MANUAL
y = 'RP'
PERFORM LI;,~iT
O T H E R W I b ~
RETURN- - JU=D LJU= x
LPA[TIx] ~ LIMIT
LAST_. S I Z E = 4
~'"E'W,',~SE
C H E C K ~
LPA[TIx] > LIMIT A[TIx] < LIMIT
LAST._SIZE = 8
3 I R EREORM L, M , T CNECK
LP
(~
LPA[TIx] ~ LIMIT
q
RETURN )
9-43
9