MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 223

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

7
7-62
10) ASSERT DATA BUFFER ENABLE (OBEN)
State 2
4) DRIVE FUNCTION CODE ON FCO-FC2
6) CACHE INHIBIT OUT (CLOUT) BECOMES VALID
7) ASSERTADDRESS STROBE ( ~ )
8) ASSERT CACHE BURST REQUEST (CBREQ)
9) ASSERT DATA STROBE (~)
2) lATCH DATA
2) N E G A T E D B E N
1) ASSERT ECS/OCS FOR ONE-HALF CLOCK
2) SET R/WTO READ
3) DRIVE ADDRESS ON AO-A31
5) DRIVE SIZE (SIZO-SIZ1) (FOUR BYTES)
1) SAMPLE CACHE INHIBIT IN (CIIN)
]) N E G A T E ASND D S E N D O F B U R S T
AND CACHE BURST ACKNOWLEDGE (CBACK)
two-clock synchronous bus cycles, the timing of DBEN may prevent its
The selected device uses R/W, SIZ0-SIZ1, A0-A1,
data on the data bus. (The first cycle must supply the long word at the
corresponding long-word boundary.) All of the byte sections (D24-D31,
drives DBEN active to enable external data buffers. In systems that use
STERM is
CIIN must be asserted at the same time as STERM. The assertion of ClIN
also has the effect of aborting the burst operation.
Figure 7-37. Burst Operation Flowchart - - Four Long Words Transferred
D16-D23, D8-D15, and D0-D7) of the data bus must be driven since the
burst operation latches 32 bits on every cycle. During $2, the processor
use. At the beginning of $2, the processor tests the level of STERM. If
STERM is recognized, the processor latches the incoming data at the end
of $2. For the burst operation to proceed, CBACK must be asserted when
S T A R T N E X T C Y C L E
recognized.
ADDRESS DEVICE
A C Q U I R E D A T A
PROCESSOR
MC68030 USER'S MANUAL
If the data for the current cycle is not to be cached,
i i ~
WHEN 4 LONG WORDS TRANSFERRED
2} PLACE DATA ON DO-D31
3) ASSERT SYNCHRONOUS TERMINATION (STERM)
4) ASSERT CACHE DURST ACKNOWLEDGE (CBACK)
2) NEGATE STERM (IF NECESSARY)
3) NEGATE CRACK (IF NECESSARY)
1) DECODE ADDRESS
t) REMOVE DATA FROM 00-D31
TERMINATE CYCLE
EXTERNAL DEVICE
PRESENT DATA
and
I
CLOUT to place the
UNTIL 4 LONG WOROS TRANSFERRED
MOTOROLA
r