MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 419

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

I0
10.3.9 Register Select ClR
10-32
10.3.80perand CIR
to the most significant byte of this CIR. The processor performs a sequence
the initial long-word transfers is aligned to the most significant byte of the
transferred. The offset from the base address of the CIR set for the register
When the coprocessor requests the transfer of an operand, the main pro-
cessor performs the transfer by reading from or writing to the 32-bit operand
$10.
The MC68030 aligns all operands transferred to and from the operand CIR
of long-word transfers to read or write any operand larger than four bytes.
operand CIR. Figure 10-21 shows the operand alignment used by the MC68030
when accessing the operand CIR.
When the coprocessor requests the transfer of one or more main processor
select CIR is $14. The format of this register depends on the primitive that
CIR. The offset from the base address of the CIR set for the operand CIR is
If the operand size is not a multiple of four bytes, the portion remaining after
registers or a group of coprocessor registers, the main processor reads the
16-bit register select CIR to identify the number or type of registers to be
is currently using it. Refer to 10.4 COPROCESSOR RESPONSE PRIMITIVES.
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Figure 10-21. Operand Alignment for Operand ClR Accesses
BYTE OPERAND
BYTE -
WORD OPERAND
OPERAND
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MC68030 USER'S MANUAL
THREE BYTE OPERAND
LONG WORD OPERAND
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NO TRANSFER
NO TRANSFER
NO TRANSFER
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NO TRANSFER
MOTOROLA
0
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