MC68030CRC33C Freescale Semiconductor, MC68030CRC33C Datasheet - Page 478

• Manufacturer Part Number: MC68030CRC33C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030CRC33C

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 128
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

MOTOROLA
Many two-word instructions (e.g., MULU.L, DIV.L, BFSET, etc.) include the
If the instruction has a source and a destination, the source EA is used for
of 6 is larger than the instruction-cache-case time of the fetch. A negative
4 - min(6,6) = - 2). This result would produce the correct execution time since
the fetch was completely overlapped and the operation was partially over-
execution time are required.
fetch immediate effective address (flea) time or the calculate immediate ef-
fective address (ciea) time in the execution time calculation. The timing for
immediate data of word length (#<data>.W) is used for these calculations.
the table lookup. If the instruction is single operand, the effective address of
that operand is used.
The following example includes multi-word instructions that refer to the fetch
immediate effective address and calculate immediate effective address tables
Note that for the head of flea #<data>.L,D1, 4 + o p head, the resulting head
number for the execution time of that portion
lapped by the same tail. No changes in the calculation for the operation
in 11.6 I N S T R U C T I O N T I M I N G TABLES,
2.
3.
1.
MULU.L (D7),DI:D2
BFCLR $6000{0:8}
DIVS.L #$10000,D3:D4
flea #<data>.W,Dn
flea #<data>.W,$XXX.W
flea #<data>.W,#<data>.L
MUL.L EA, Dn
BFCLR Mem(<5 bytes)
DIVS.L EA,Dn
2.
3.
MC68030 USER'S MANUAL
1.
MULU.L
DIVS.L
BFCLR
Instruction
(D7),DI:D2
$6000{0:8}
#$10000,D3:D4
2 + op head
6 - op head
2(op head)
0(op head)
Head
4
4
6
6
could result (e.g.,
Tail
0
0
0
0
2
0
0
0
CC
44
90
14
2
6
6
6
2
11-15
11