DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 117

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

is written to the TFDL, it will be multiplexed serially (LSB first) into the proper position in the outgoing
T1 data stream. After the full 8 bits has been shifted out, the framer will signal the host microcontroller
that the buffer is empty and that more data is needed by setting the SR2.3 bit to a 1. The INT will also
toggle low if enabled via IMR2.3. The user has 2 ms to update the TFDL with a new value. If the TFDL
is not updated, the old value in the TFDL will be transmitted once again. The framer also contains a zero
stuffer, which is controlled via the CCR2.4 bit. In both ANSI T1.403 and TR54016, communications on
the FDL follows a subset of a LAPD protocol. The LAPD protocol states that no more than five 1’s
should be transmitted in a row so that the data does not resemble an opening or closing flag (01111110)
or an abort signal (11111111). If enabled via CCR2.4, the framer will automatically look for five 1’s in a
row. If it finds such a pattern, it will automatically insert a 0 after the five 1’s. The CCR2.0 bit should
always be set to a 1 when the framer is inserting the FDL. More on how to use the DS2196 in FDL
applications is covered in a separate Application Note.
TFDLA: TRANSMIT FDL REGISTER for FORMATTER A (Address = 7E Hex)
TFDLB: TRANSMIT FDL REGISTER for FORMATTER B (Address = FE Hex)
The Transmit FDL Register (TFDL) contains the Facility Data Link (FDL) information that is to be
inserted on a byte basis into the outgoing T1 data stream. The LSB is transmitted first.
18.3 D4/SLC–96 OPERATION
In the D4 framing mode, the framer uses the TFDL register to insert the Fs framing pattern. To allow the
device to properly insert the Fs framing pattern, the TFDL register at address 7Eh must be programmed to
1Ch and the following bits must be programmed as shown: TCR1.2=0 (source Fs data from the TFDL
register) CCR2.5=1 (allow the TFDL register to load on multiframe boundaries)
Since the SLC–96 message fields share the Fs–bit position, the user can access the message fields via the
TFDL and RFDL registers. Please see the separate Application Note for a detailed description of how to
implement a SLC–96 function.
[Also used to insert Fs framing pattern in D4 framing mode; see Section 18.3]
TFDL7
(MSB)
SYMBOL
TFDL7
TFDL0
TFDL6
POSITION
TFDL.7
TFDL.0
TFDL5
NAME AND DESCRIPTION
MSB of the FDL code to be transmitted
LSB of the FDL code to be transmitted
TFDL4
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TFDL3
TFDL2
TFDL1
TFDL0
(LSB)
DS2196