DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 17

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

Signal Name:
Signal Description:
Signal Type:
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not used, this
pin should be pulled high.
Signal Name:
Signal Description:
Signal Type:
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this pin should be
pulled high. This pin has an internal pull-up.
Signal Name:
Signal Description:
Signal Type:
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this pin should be left
open circuited.
Signal Name:
Signal Description:
Signal Type:
This signal is used to synchronously reset the test access port controller. At power up, JTRST must be set low and
then high. This action will set the device into the boundary scan bypass mode allowing normal device operation.
If boundary scan is not used, this pin should be held low. This pin has an internal pull-up.
Signal Name:
Signal Description:
Signal Type:
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various defined IEEE
1149.1 states. If not used, this pin should be pulled high. This signal has an internal pull-up.
Line Interface Pins
Signal Name:
Signal Description:
Signal Type:
A 1.544 MHz (±50 ppm) clock source with TTL levels is applied at this pin. This clock is used internally for both
clock/data recovery and for jitter attenuation. This clock is also used to source AIS within the LIU.
Signal Name:
Signal Description:
Signal Type:
Analog inputs for clock recovery circuitry. These pins connect via a 1:1 transformer to the T1 line. See Section 19
for details.
Signal Name:
Signal Description:
Signal Type:
Analog line driver outputs. These pins connect via a 1:2 step–up transformer to the T1 line. See Section 19 for
details.
Signal Name:
Signal Description:
JTCLK
JTAG IEEE 1149.1 Test Serial Clock
Input
JTDI
JTAG IEEE 1149.1 Test Serial Data Input
Input
JTDO
JTAG IEEE 1149.1 Test Serial Data Output
Output
JTRST*
JTAG IEEE 1149.1 Test Reset
Input
JTMS
JTAG IEEE 1149.1 Test Mode Select
Input
MCLK
Master Clock Input
Input
RTIP & RRING
Receive Tip and Ring
Input
TTIP & TRING
Transmit Tip and Ring
Output
LFSYNC
LIU Frame Sync
17 of 157