DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 98

• Manufacturer Part Number: DS2196
• Description: T1 Dual Framer LIU
• Manufacturer: Dallas Semiconducotr

Table 16-1: Error Rate Options
NOE1A: NUMBER of ERRORS 1 FRAMER A (Address = 81 Hex)
NOE1B: NUMBER of ERRORS 1 FRAMER B (Address = 86 Hex)
NOE2A: NUMBER of ERRORS 2 FRAMER A (Address = 82 Hex)
NOE2B: NUMBER of ERRORS 2 FRAMER B (Address = 87 Hex)
Number Of Errors Registers.
generated. Up to 1023 errors can be generated. The Host will load the number of errors to be generated
into the NOE registers. The Host can also update the number of errors to be created by first loading the
prescribed value into the NOE registers and then toggling the WNOE bit in the Error Rate Control
registers. Refer to Table 16-2 for examples.
ER3
(MSB)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
C7
SYMBOL
–
ER2
C9
C0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
ER1
C6
–
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ER0
POSITION
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
NOE2.1
NOE1.0
C5
–
No errors inserted
1 in 16
1 in 32
1 in 64
1 in 128
1 in 256
1 in 512
1 in 1024
1 in 2048
1 in 4096
1 in 8192
1 in 16384
1 in 32768
1 in 65536
1 in 131072
1 in 262144
Error Rate
The Number Of Error registers determines how many errors will be
C4
–
NAME AND DESCRIPTION
MSB of the 10–bit Number of Errors Counter
LSB of the 10–bit Number of Errors Counter
C3
–
98 of 157
C2
–
C1
C9
(LSB)
C0
C8
NOE1
NOE2