DS2196 Dallas Semiconducotr, DS2196 Datasheet - Page 155
DS2196
Manufacturer Part Number
DS2196
Description
T1 Dual Framer LIU
Manufacturer
Dallas Semiconducotr
Datasheet
1.DS2196.pdf
(157 pages)
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Figure 22-10: TRANSMIT SIDE AC TIMING
TCHCLK
TCHBLK
TSYNC
TSYNC
TLCLK
Notes:
1. TSYNC is in the output mode (TCR2.2 = 1).
2. TSYNC is in the input mode (TCR2.2 = 0).
3. TSER is sampled on the falling edge of TCLK when the transmit side elastic store is disabled.
4. TCHCLK and TCHBLK are synchronous with TCLK when the transmit side elastic store is disabled.
5. TLINK is only sampled during F-bit locations.
6. No relationship between TCHCLK and TCHBLK and the other signals is implied.
TLINK
TCLK
TSER
1
2
5
t
R
t D2
t D2
t
F t
D2
t
SU
t
SU
t D2
t SU
t
HD
t
HD
t HD
155 of 157
t
CL
t
CP
t
CH
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