ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 103

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

SERIAL PERIPHERAL INTERFACE (cont’d)
10.4.6 Low Power Modes
10.4.6.1 Using the SPI to wake up the device
from Halt mode
In slave configuration, the SPI is able to wake up
the device from Halt mode through a SPIF inter-
rupt. The data received is subsequently read from
the SPIDR register when the software is running
(interrupt vector fetch). If multiple data transfers
have been performed before software clears the
SPIF bit, then the OVR bit is set by hardware.
Note: When waking up from Halt mode, if the SPI
remains in Slave mode, it is recommended to per-
Mode
Wait
Halt
No effect on SPI.
SPI interrupt events cause the device to exit
from Wait mode.
SPI registers are frozen.
In Halt mode, the SPI is inactive. SPI opera-
tion resumes when the device is woken up by
an interrupt with “exit from Halt mode” capa-
bility. The data received is subsequently read
from the SPIDR register when the software is
running (interrupt vector fetching). If several
data are received before the wake-up event,
then an overrun error is generated. This error
can be detected after the fetch of the inter-
rupt routine that woke up the Device.
Description
form an extra communications cycle to bring the
SPI from Halt mode state to normal state. If the
SPI exits from Slave mode, it returns to normal
state immediately.
Caution: The SPI can wake up the device from
Halt mode only if the Slave Select signal (external
SS pin or the SSI bit in the SPICSR register) is low
when the device enters Halt mode. So, if Slave se-
lection is configured as external (see
10.4.3.2), make sure the master drives a low level
on the SS pin when the slave enters Halt mode.
10.4.7 Interrupts
Note: The SPI interrupt events are connected to
the same interrupt vector (see Interrupts chapter).
They generate an interrupt if the corresponding
Enable Control Bit is set and the interrupt mask in
the CC register is reset (RIM instruction).
SPI End of
Transfer Event
Master Mode
Fault Event
Overrun Error
Interrupt Event
MODF
Event
SPIF
OVR
Flag
ST7MC1xx/ST7MC2xx
Control
Enable
SPIE
Bit
from
Wait
Exit
Yes
Section
103/309
from
Exit
Halt
Yes
No
1