ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 290

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7MC1xx/ST7MC2xx
14 ST7MC DEVICE CONFIGURATION AND ORDERING INFORMATION
Each device is available for production in ROM
versions and in user programmable versions
(FLASH) as well as in factory coded versions
(FASTROM). ST7MC are ROM devices. ST7PMC
devices are Factory Advanced Service Technique
ROM (FASTROM) versions: they are programmed
Flash devices.
14.1 FLASH OPTION BYTES
The option bytes allow the hardware configuration
of the microcontroller to be selected. They have no
address in the memory map and can be accessed
only in programming mode (for example using a
standard ST7 programming tool). The default con-
tent of the FLASH is fixed to FFh. This means that
all the options have “1” as their default value.
OPTION BYTE 0
OPT7= WDG HALT Watchdog and Halt mode
This option bit determines if a RESET is generated
when entering Halt mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode
OPT6= WDG SW Hardware or software watchdog
This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
OPT5 = CKSEL Clock Source Selection.
0: PLL clock selected
1: Oscillator clock selected
Note 1: Even if PLL clock is selected, a clock signal must
always be present (refer to
OPT4:3= VD[1:0] Voltage detection
These option bits enable the voltage detection
block (LVD, and AVD).
290/309
Default
value
Selected Low Voltage Detector
LVD On and AVD Off
7
LVD and AVD On
1
WDG
1
STATIC OPTION BYTE 0
1)
1
Figure 13. on page
1
1
VD
0
1
VD1
0
0
1
28)
VD0
1
0
1
1
0
ST7FMC Flash devices are shipped to customers
with a default content (FFh), while ROM/FAS-
TROM factory coded parts contain the code sup-
plied by the customer. This implies that Flash de-
vices have to be configured by the customer using
the Option Bytes while the ROM devices are facto-
ry-configured.
OPT2 = RSTC RESET clock cycle selection
This option bit selects the number of CPU cycles
applied during the RESET phase and when exiting
Halt mode. For resonator oscillators, it is advised
to select 4096 due to the long crystal stabilization
time.
0: Reset phase with 4096 CPU cycles
1: Reset phase with 256 CPU cycles
Note: When the PLL clock is selected (CKSEL=0),
the reset clock cycle selection is forced to 4096
CPU cycles.
OPT1= DIV2 Divider by 2
1: DIV2 divider disabled with OSCIN = 8MHz
0: DIV2 divider enabled (in order to have 8 MHz re-
OPT0= FMP_R Flash memory read-out protection
Readout protection, when selected provides a pro-
tection against program memory content extrac-
tion and against write access to Flash memory.
This protection is based on a read/write protection
of the memory in test modes and ICP mode. Eras-
ing the option bytes when the FMP_R option is se-
lected causes the whole user memory to be
erased first and the device can be reprogrammed.
Refer to the ST7 Flash Programming Reference
Manual and
tails.
0: Read-out protection enabled
1: Read-out protection disabled
quired for the PLL with OSCIN =16 Mhz))
2
1
7
Selected Low Voltage Detector
PKG
1
1
LVD and AVD Off
section 4.3.1 on page 22
STATIC OPTION BYTE 1
0
1
1
1
1
VD1
for more de-
1
1
1
MCO
VD0
0
0
1
1