ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 183

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

MOTOR CONTROLLER (Cont’d)
A logic block manages capture operations de-
pending on the sensor type. A capture is initiated
on an active edge (“Tacho capture” event) when
using a tachogenerator.
If an encoder is used, the capture is triggered on
two events depending on the Encoder Capture
Mode bit (ECM) in the MZFR register:
The clock source of the counter is selected de-
pending on sensor type:
In order to optimize the accuracy of the measure-
ment for a wide speed range, the auto-updated pr-
escaler functionality is used with slight modifica-
tions compared to Sensor/Sensorless Modes (re-
fer to
– When the [MTIM:MTIML] timer value reaches
Figure 103. Auto-updated prescaler functional diagram
FFFFh, the prescaler is automatically increment-
ed in order to slow down the counter and avoid
an overflow. To keep consistent values, the
MTIM and MTIML registers are shifted right (di-
– Reading the MSB of the counter in manual
– Interrupt from the Real-time Clock in automat-
– Motor Control Peripheral clock (16 MHz) with
– Encoder Clock
mode (ECM = 1)
ic mode (ECM = 0)
tachogenerator or Hall sensors
Figure 103
[MTIM:MTIML] Timer Overflow
(MTIM = MTIML = FFh)
and
Counter = Counter/2
Slow-down control
Ratio = Ratio + 1
Ratio < Fh?
Table
Begin
End
Yes
38).
No
– When a capture event occurs, if the
– If the prescaler contents reach the value 0, it can
– If the prescaler contents reach the value 15, it
The only automatically updated registers for the
Speed Sensor Mode are MTIM and MTIML. Ac-
cess to Delay manager registers in Speed Sensor
Mode is summarised in
vided by two). The RPI bit in the MISR register is
set and an interrupt is generated (if RIM is set).
[MTIM:MTIML] timer value is below 5500h, the
prescaler is automatically decremented in order
to speed up the counter and keep precision bet-
ter than 0.005% (1/5500h). The MTIM and
MTIML registers are shifted left (multiplied by
two). The RMI bit in the MISR register is set and
an interrupt is generated if RIM is set.
no longer be automatically decremented, the
[MTIM:MTIML] timer continues working with the
same prescaler value, i.e. with a lower accuracy.
No RMI interrrupt can be generated.
can no longer be automatically incremented.
When the timer reaches the value FFFFh, the pr-
escaler and all the relevant registers remain un-
changed and no interrupt is generated, the timer
clock is disabled, and its contents stay at FFFFh.
The capture logic block still works, enabling the
capture of the maximum timer value.
Capture with [MTIM:MTIML] Timer < 5500h
Speed-up control
Ratio = Ratio - 1
Counter = 0
(MZREG < 55h)
Ratio > 0?
Begin
End
Yes
ST7MC1xx/ST7MC2xx
Table
41.
No
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