ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 222

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
POLARITY REGISTER (MPOL)
Read/Write (some bits write-once)
Reset Value: 0011 1111 (3Fh)
Bit 7 = ZVD: Z vs D edge polarity.
0: Zero-crossing and End of Demagnetisation
1: Zero-crossing and End of Demagnetisation
Bit 6 = REO: Read on High or
0: Read the BEMF signal on High channels
1: Read on
Note: This bit always has to be configured whatev-
er the sampling method.
Bits 5:0 = OP[5:0]*: Output channel polarity.
These bits are used together with the OO
in the MPHST register to control the output chan-
nels.
0: Output channel is Active Low
1: Output channel is Active High.
* Write-once bits; once write-accessed these bits
cannot be re-written unless the processor is reset
(See “Caution: Access to write-once bits” on
page 220.).
Table 75. Output Channel State Control
Warning: OP[5:0] bits in the MPOL register must
be configured as required by the application be-
fore enabling the MCO[5:0] outputs with the MOE
bit in the MCRA register.
222/309
OP[5:0] bit
ZVD
have opposite edges
have same edge
7
0
0
1
1
REO
6
Low
OP5
5
OO[5:0] bit
channels
0
1
0
1
OP4
4
OP3
3
Low
0 (PWM possible)
1 (PWM possible)
OP2
2
MCO[5:0] pin
channel bit
1 (Off)
0 (Off)
OP1
1
[5:0]
OP0
0
bits