ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 95

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.
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not possible at maximum frequency due to the
software overhead for clearing status flags and to
initiate the next transmission sequence.
Full duplex synchronous transfers (on three
lines)
Simplex synchronous transfers (on two lines)
Master or slave operation
6 master mode frequencies (f
f
SS Management by software or hardware
Programmable clock polarity and phase
End of transfer interrupt flag
Write collision, Master Mode Fault and Overrun
flags
CPU
In slave mode, continuous transmission is
/2 max. slave mode frequency (see note)
(cont’d)
CPU
/4 max.)
Figure 55 on page 96
interface (SPI) block diagram. There are three reg-
isters:
The SPI is connected to external devices through
four pins:
– SPI Control Register (SPICR)
– SPI Control/Status Register (SPICSR)
– SPI Data Register (SPIDR)
– MISO: Master In / Slave Out data
– MOSI: Master Out / Slave In data
– SCK: Serial Clock out by SPI masters and in-
– SS: Slave select:
put by SPI slaves
This input signal acts as a ‘chip select’ to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master Device.
shows the serial peripheral
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