ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 117

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

LINSCI™ SERIAL COMMUNICATION INTERFACE (SCI Mode) (cont’d)
10.5.8 SCI Mode Register Description
STATUS REGISTER (SCISR)
Read Only
Reset Value: 1100 0000 (C0h)
Bit 7 = TDRE
This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
Bit 6 = TC
This bit is set by hardware when transmission of a
character containing Data is complete. An inter-
rupt is generated if TCIE = 1 in the SCICR2 regis-
ter. It is cleared by a software sequence (an ac-
cess to the SCISR register followed by a write to
the SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a Pre-
amble or a Break.
Bit 5 = RDRF
This bit is set by hardware when the content of the
RDR register has been transferred to the SCIDR
register. An interrupt is generated if RIE = 1 in the
SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
Bit 4 = IDLE
This bit is set by hardware when an Idle Line is de-
tected. An interrupt is generated if the ILIE = 1 in
the SCICR2 register. It is cleared by a software se-
quence (an access to the SCISR register followed
by a read to the SCIDR register).
0: No Idle Line is detected
1: Idle Line is detected
Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (that is, a new idle line
occurs).
TDRE
7
TC
RDRF
IDLE
OR
1)
NF
1)
FE
1)
PE
0
1)
Bit 3 = OR
The OR bit is set by hardware when the word cur-
rently being received in the shift register is ready to
be transferred into the RDR register whereas
RDRF is still set. An interrupt is generated if
RIE = 1 in the SCICR2 register. It is cleared by a
software sequence (an access to the SCISR regis-
ter followed by a read to the SCIDR register).
0: No Overrun error
1: Overrun error detected
Note: When this bit is set, RDR register contents
will not be lost but the shift register will be overwrit-
ten.
Bit 2 = NF Character Noise flag
This bit is set by hardware when noise is detected
on a received character. It is cleared by a software
sequence (an access to the SCISR register fol-
lowed by a read to the SCIDR register).
0: No noise
1: Noise is detected
Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.
Bit 1 = FE Framing error
This bit is set by hardware when a desynchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by a software sequence (an
access to the SCISR register followed by a read to
the SCIDR register).
0: No Framing error
1: Framing error or break character detected
Note: This bit does not generate an interrupt as it
appears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both a frame error and
an overrun error, it will be transferred and only the
OR bit will be set.
Bit 0 = PE Parity error
This bit is set by hardware when a byte parity error
occurs (if the PCE bit is set) in receiver mode. It is
cleared by a software sequence (a read to the sta-
tus register followed by an access to the SCIDR
data register). An interrupt is generated if PIE = 1
in the SCICR1 register.
0: No parity error
1: Parity error detected
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