ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 89

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 =
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
Bit 6 =
0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the
Bit 5 =
0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF
ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
7
ICF1 or ICF2 bit of the SR register is set.
OCF1 or OCF2 bit of the SR register is set.
bit of the SR register is set.
Input Capture Interrupt Enable.
Timer Overflow Interrupt Enable.
Output Compare Interrupt Enable.
(Cont’d)
0
Bit 4 =
This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the
Bit 3 =
This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if
Bit 2 =
This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.
Bit 1 =
This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.
Bit 0 =
The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.
OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.
the OC1E bit is set and even if there is no suc-
cessful comparison.
Input Edge 1.
Forced Output Compare 2.
Forced Output Compare 1.
Output Level 2.
Output Level 1.
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