ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 83

no-image

ST7FMC1K2B3

Manufacturer Part Number
ST7FMC1K2B3
Description
Manufacturer
STMICROELECTRONICS [STMicroelectronics]
Datasheet
16-BIT TIMER (Cont’d)
Notes:
1. After a processor write cycle to the OCiHR reg-
2. If the OCiE bit is not set, the OCMPi pin is a
3. In both internal and external clock modes, OCFi
4. The output compare functions can be used both
5. The value in the 16-bit OC
Figure 50. Output Compare Block Diagram
16-bit
ister, the output compare function is inhibited
until the OCiLR register is also written.
general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt
could be generated if the OCIE bit is set.
and OCMPi are set while the counter value
equals the OCiR register value (see
for an example with f
example with f
in OPM or PWM mode.
for generating external events on the OCMPi
pins even if the input capture mode is also
used.
OLVi bit should be changed after each suc-
cessful comparison in order to control an output
waveform or establish a new elapsed timeout.
16 BIT FREE RUNNING
OC1R Register
OUTPUT COMPARE
16-bit
CIRCUIT
OC2R Register
COUNTER
16-bit
CPU/4
). This behavior is the same
CPU/2
and
i
R register and the
Figure 52
OC1E
OCIE
Figure 51
OC2E
OCF1
for an
FOLV2 FOLV1
Forced Compare Output capability
When the FOLVi bit is set by software, the OLVLi
bit is copied to the OCMPi pin. The OLVi bit has to
be toggled in order to toggle the OCMPi pin when
it is enabled (OCiE bit=1). The OCFi bit is then not
set by hardware, and thus no interrupt request is
generated.
FOLVLi bits have no effect in both one pulse mode
and PWM mode.
(Control Register 2) CR2
(Control Register 1) CR1
OCF2
CC1
(Status Register) SR
OLVL2
CC0
0
0
OLVL1
0
ST7MC1xx/ST7MC2xx
Latch
Latch
1
2
OCMP1
OCMP2
Pin
Pin
83/309
1

Related parts for ST7FMC1K2B3