ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 204

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
■
This mode is useful for MCMP0 values ranging
from 9 bits to 12 bits.
Compare 0 and Compare U, V, W should be load-
ed). It requires loading two bytes in the MCMPxH
and MCMPxL registers (i.e. MCMP0, MCMPU,
MCMPV and MCMPW 16-bit registers) following
the sequence described below:
– write to the MCMPxL register (LSB) first
– then write to the MCMPxH register (MSB).
The 16-bit value is then ready to be transferred in
the active register as soon as an update event oc-
curs. This sequence is necessary to avoid poten-
tial conflicts with update interrupts causing the
hardware transfer from preload to active registers:
if an update event occurs in the middle of the
above sequence, the update is effective only when
the MSB has been written.
■
This mode is useful whenever the MCMP0 value is
less or equal to 8-bits. It allows significant CPU re-
Figure 121. Comparison between 12-bit and 8-bit PWM mode
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1
12-bit PWM mode
12-bit Mode (PMS bit = 0 in the MPCR register)
8-bit PWM mode (PMS bit = 1 in MPCR register)
8-bit PWM mode
(PMS bit = 0)
(PMS bit = 1)
Figure 121
OvfX
MCMP0H
MCMPxH
MCMP0H
MCMPxH
Ext
b7
b7
b7
b7
MPCR
b7
OvfU
presents the way
OvfV
OvfW
b0
b0
b0
b0
b0
source savings when computing three-phase duty
cycles during PWM interrupt routines. In this
mode, the Compare 0 and Compare U, V, W reg-
isters have the same size (8 bits). The extension of
the MCMPx registers is done in using the OVFx
bits in the MPCR register (refer to
These bits force the related duty-cycles to 100%
and are reset by hardware on occurence of a
PWM update event.
Note about read access to registers with
preload: during read accesses, values read are
the content of the preload registers, not the active
registers.
Note about compare register active bit loca-
tions: the 13 active bits of the MCMPx registers
are left-aligned. This allows temporary calculations
to be done with 16-bit precision, round-up is done
automatically to the 13-bit format when loading the
values of the MCMPx registers.
Note about MCMP0x registers: the configuration
MCMP0H=MCMP0L=0 is not allowed
MCMP0L
MCMPxL
MCMP0L
MCMPxL
b7
b7
b7
b7
Ext
Equivalent bit location
Bit extending comparison range
Bit not available
b0
b0
b0
b0
PWM frequency
PWM frequency
Phase x duty
Phase x duty
cycle set-up
cycle set-up
set-up
set-up
Figure
121).