ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 267

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

12.9 CONTROL PIN CHARACTERISTICS
12.9.1 Asynchronous RESET Pin
Subject to general operating conditions for V
Notes:
1. Data based on characterization results, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
(I/O ports and control pins) must not exceed I
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below t
5. The reset network protects the device against parasitic resets.
t
w(RSTL)out
t
t
Symbol
h(RSTL)in
g(RSTL)in
R
V
V
V
V
I
hys
IO
ON
OL
IH
IL
IO
current sunk must always respect the absolute maximum rating specified in
Input low level voltage
Input high level voltage
Schmitt trigger voltage hysteresis
Output low level voltage
Driving current on RESET pin
Weak pull-up equivalent resistor
Generated reset pulse duration
External reset pulse hold time
Filtered glitch duration
Parameter
h(RSTL)in
5)
3)
4)
can be ignored.
VSS
2)
.
DD
V
V
Internal reset sources
, f
DD
IN
OSC
=
=5V
V
Conditions
SS,
, and T
V
I
I
DD
IO
IO
=+5mA
=+2mA
=5V
A
unless otherwise specified.
0.7xV
Min
2.5
50
DD
Section 12.2.2
ST7MC1xx/ST7MC2xx
Typ
0.5
0.2
450
80
30
1
2
0.3xV
and the sum of I
Max
150
1.2
0.5
DD
267/309
Unit
mA
kΩ
ns
μs
μs
V
V
V
IO