ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 168

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

ST7MC1xx/ST7MC2xx
MOTOR CONTROLLER (Cont’d)
10.6.7 Delay Manager
Figure 91. Overview of MTIM Timer in Switched and Autoswitched Mode
This part of the MTC contains all the time-related
functions, its architecture is based on an 8-bit shift
left/shift right timer shown in
timer includes:
– An auto-updated prescaler
– A capture/compare register for simulated de-
– Two cascaded capture and one compare regis-
– An 8x8 bit multiplier for auto computing the next
– One compare register for phase commutation
168/309
1
Z
magnetization simulation (MDREG)
ters (MZREG and MZPRV) for storing the times
between two consecutive BEMF zero crossings
(Z
tion (Z
commutation time
generation (MCOMP)
H
H
/ Z
§
= Register updated on R event
events) and for zero-crossing event simula-
S
Z
MZPRV [Z
S
H
)
MZREG [Z
MCOMP [C
MCRC register
n-1
SZ bit
]
§
n
]
§
Compare
n+1
MCRC register
]
§
Figure
SC bit
Filter /D
MZFR register
ZWF[3:0]
8-bit Up Counter MTIM
91. The MTIM
Compare
Z
S
T
ck
ratio
8
C
H
/ C
MCRB register
The MTIM timer module can work in two main
modes when driving synchronous motors in six-
steps mode.
In switched mode the user must process the step
duration and commutation time by software.
In autoswitched mode the commutation action is
performed automatically depending on the rotor
position information and register contents. This is
called the hardware commutation event C
enabled by the SC bit in the MCRC register, com-
mutation can also be simulated by writing a value
directly in the MCOMP register that is compared
with the MTIM value. This is called simulated com-
mutation C
simulated events” on page 175.).
Both in switched mode and autoswitched mode , if
the SC bit in the MCRC register is set (software
commutation enabled), no comparison between
S
§
SDM* bit
D
Compare
H
S
MDREG [D
(See “Built-in Checks and Controls for
clr
Filter /C
MDFR register
DWF[3:0]
C
D
Z
H,S
H,S
S,H
D
MCRA register
SWA bit
n
S
]
§
0
1
To interrupt generator
To interrupt generator
To interrupt generator
C
Z
H
. When