ST7FMC1K2B3 STMICROELECTRONICS [STMicroelectronics], ST7FMC1K2B3 Datasheet - Page 171

• Manufacturer Part Number: ST7FMC1K2B3
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

MOTOR CONTROLLER (Cont’d)
10.6.7.2 Autoswitched Mode
In this mode, using the hardware commutation
event C
MCOMP register content is automatically comput-
ed in real-time as described below and in
93.
The C (either C
contents of the MTIM timer.
When a Z
captured in the MZREG register, the previous cap-
tured value is shifted into the MZPRV register and
the MTIM timer is reset. See
When a Z
MZREG register is shifted into the MZPRV register
and the MTIM timer is reset.
One of these two registers, (when the SC bit = 0 in
the MCRC register and depending on the DCB bit
in the MCRA register), is multiplied with the con-
tents of the MWGHT register and divided by 256.
The result is loaded in the MCOMP compare reg-
ister, which automatically triggers the next hard-
ware commutation (C
Note: The result of the 8*8 bit multiplication, once
written in the MCOMP register is compared with
the current MTIM value to check that the MCOMP
value is not already less than the MTIM value due
to the multiplication time. If MCOMP<=MTIM, a C
event is generated immediately and the MCOMP
value is overwritten by the MTIM value.
Table 39. Multiplier Result
After each shift operation the multiply is recomput-
ed for greater precision.
Using either the MZREG or MZPRV register de-
pends on the motor symmetry and type.
The MWGHT register gives directly the phase shift
between the motor driven voltage and the BEMF.
This parameter generally depends on the motor
and on the speed.
Setting the SC bit in the MCRC register enables
the simulated commutation event (C
This means that a write access is possible to the
MCOMP register and the MTIM value will be com-
pared directly with the value written by software in
the MCOMP register to generate the C
The comparison is enabled as soon as a write ac-
cess is done to the MCOMP register. This means
that if the SC bit is set and no write access is done
to the MCOMP register, the C event will never oc-
DCB bit
0
1
H
H
S
(SC bit reset in MCRC register), the
event occurs the MTIM timer value is
event occurs, the value written in the
MCOMP = MWGHT x MZREG / 256
MCOMP = MWGHT x MZPRV / 256
S
or C
H
H
Commutation Delay
) event has no effect on the
event).
Figure
73.
S
) generation.
S
Figure
event.
H
cur because no comparison will be done between
MCOMP and MTIM. Therefore, it is recommended
in autoswitched mode, when using software com-
mutation feature (SC bit is set) and for a normal
event sequence, the corresponding value to be
put in MCOMP has to be written during the Z inter-
rupt routine (because MTIM has just been reset),
so that there is no spurious comparison. If the SC
bit is set during a Z event interrupt, then , the result
of the 8*8 bits hardware multiplication can be over-
written by software in the MCOMP register. When
simulated commutation mode is enabled, the
event sequence is no longer respected, meaning
that the peripheral will accept consecutive commu-
tation events and not necessarily wait for a D
event after a C
register can be written immediately after the previ-
ous C event, in the C interrupt service routine for
example.
Figure 93. C
Note 1: An overflow of the MTIM timer generates
an RPI interrupt if the RIM bit is set.
Note 2: When simulated commutation mode is en-
abled, the D and Z event are not ignored by the
peripheral, this means that if a Z event happens,
the MTIM 8 bit internal counter will be reset.
Note 3: To generate consecutive simulated com-
mutations (C
written in the MCOMP register only after a C event
MCRA Register
MCRC register
§
= Register updated on R event
MCRA Register
Z
SWA bit =1 &
H
SC bit =0
DCB bit
/Z
S
MWGHT [a
MZPRV [Z
MZREG [Z
MCOMP [C
H
S
), the successive value has to be
Processor Block
s
event. In this case the MCOMP
n-1
n+1
8
n
]
§
]
n+1
]
§
A x B / 256
]
§
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