W7100A WIZnet, W7100A Datasheet - Page 40

• Manufacturer Part Number: W7100A
• Description: 8-bit Microcontrollers - MCU 8051 CORE+HARDWIRED TCP/IP+MAC+PHY
• Manufacturer: WIZnet

Specifications of W7100A

• Rohs: yes
• Core: 8051
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 25 MHz
• Program Memory Size: 255 B
• Data Ram Size: 64 KB
• On-chip Adc: No
• Operating Supply Voltage: 3 V to 3.6 V
• Operating Temperature Range: - 40 C to + 80 C
• Package / Case: LQFP-100
• Mounting Style: SMD/SMT
• Interface Type: UART
• Program Memory Type: Flash

© Copyright 2011 WIZnet Co., Inc. All rights reserved.
WCONF(0xFF): W7100A configuration register
Note:
Note: CLK_CNT is 32bit SFR, reset value is 0, increase its value at every core clock. T
CLKCNT0(0xDC): W7100A core clock count register bit0 ~ 7.
ex> usage of mode selection using MODE2 ~ 0
7
RB
Bit7
PHYCONF |= 0x08;
PHYCONF &= 0xF8; //
PHYCONF |= 0x20;
Delay();
PHYCONF &= ~(0x20);
7
PHY_PWDN: 1- Power down mode: turn off the embedded Ethernet PHY to save
MODE_EN : 1 – Configure W7100A operation mode using the MODE2 ~ 0 bit / 0 – d
MODE2 ~ 0: Please refer to the section 1.4.2 ‘Pin Description’ PM2 ~ 0 pin settin
ISPEN
EM[2:0]
FB
BE
RB
-
6
ISPEN
Bit6
6
// Delay for reset timing(refer to the section 10 ‘Electrical Specification’)
Memory Access’.
ng this bit, set this bit ‘1’ first, then manually clear to ‘0’ after the
reset time. About the reset time please refer to the section 10 ‘Elec
trical Specification’.
power consumption
on’t use MODE2 ~ 0 bit.
and MODE2 ~ 0 bits to configure the operation mode of W7100A
g value, MODE2 ~ 0 bit are same as PM2 ~ 0 pin.
: Reserved, must be set to ‘0’
: 0 – No Reboot / 1 – Reboot after the ISP done (APP Entry(0xFFF7 ~
0xFFFF) RD/WR Enable)
: 0 – Enable ISP in Boot built in W7100A / 1 – Disable
: External memory mode, please refer to the section 2.3 ‘External Data
: FLASH Busy Flag for ISP. Read only.
: Boot Enable (1 – Boot Running / 0 – Apps Running). Read only.
0 – Normal operation mode.
5
EM2
Bit5
// MODE_EN bit enable
// Set the PHY_RSTn bit (reset bit)
Figure 2.31 W7100A Configuration Register
5
// Clear the PHY_RSTn bit
Figure 2.32 Core clock count register
MODE2 ~ 0 value is 0 (normal mode); Auto configuration mode
4
EM1
Bit4
4
CLK_CNT0 (0xDC)
3
EM0
WCONF (0xFF)
Bit3
In the QFN 64pin package, must use this bit
3
2
Reserved
Bit2
2
1
FB
Bit1
1
0
BE
Ver. 1.12
Bit0
0
Reset
0x00
Reset
0x00
40