ATMEGA324P-A15MZ Atmel, ATMEGA324P-A15MZ Datasheet - Page 175

• Manufacturer Part Number: ATMEGA324P-A15MZ
• Description: MCU AVR 32KB FLASH 15MHZ 44-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 1K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Overview of the
TWI Module
SCL and SDA Pins
Bit Rate Generator
Unit
Bus Interface Unit
2503N–AVR–06/08
The TWI module is comprised of several submodules, as shown in
in a thick line are accessible through the AVR data bus.
Figure 84. Overview of the TWI Module
These pins interface the AVR TWI with the rest of the MCU system. The output drivers contain a
slew-rate limiter in order to conform to the TWI specification. The input stages contain a spike
suppression unit removing spikes shorter than 50 ns. Note that the internal pullups in the AVR
pads can be enabled by setting the PORT bits corresponding to the SCL and SDA pins, as
explained in the I/O Port section. The internal pull-ups can in some systems eliminate the need
for external ones.
This unit controls the period of SCL when operating in a Master mode. The SCL period is con-
trolled by settings in the TWI Bit Rate Register (TWBR) and the Prescaler bits in the TWI Status
Register (TWSR). Slave operation does not depend on Bit Rate or Prescaler settings, but the
CPU clock frequency in the slave must be at least 16 times higher than the SCL frequency. Note
that slaves may prolong the SCL low period, thereby reducing the average TWI bus clock
period. The SCL frequency is generated according to the following equation:
•
•
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
TWBR = Value of the TWI Bit Rate Register
TWPS = Value of the prescaler bits in the TWI Status Register
Pull-up resistor values should be selected according to the SCL frequency and the capacitive bus
line load. See
Slew-rate
Address Match Unit
Arbitration detection
Control
START / STOP
Address Comparator
Address Register
Control
SCL
(TWAR)
Table 119 on page 290
Spike
Filter
Bus Interface Unit
SCL frequency
Spike Suppression
Address/Data Shift
Register (TWDR)
Slew-rate
Control
for value of pull-up resistor.
=
SDA
Status Register
---------------------------------------------------------- -
16
CPU Clock frequency
Ack
Spike
Filter
(TWSR)
+
2(TWBR) 4
State Machine and
Control Unit
Status control
⋅
TWPS
Control Register
Bit Rate Generator
(TWCR)
Figure
Bit Rate Register
Prescaler
ATmega32(L)
(TWBR)
84. All registers drawn
TWI Unit
175