ATMEGA324P-A15MZ Atmel, ATMEGA324P-A15MZ Datasheet - Page 51

• Manufacturer Part Number: ATMEGA324P-A15MZ
• Description: MCU AVR 32KB FLASH 15MHZ 44-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 1K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reading the Pin Value
2503N–AVR–06/08
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b11) as an intermediate step.
Table 20
Table 20. Port Pin Configurations
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
tute a synchronizer. This is needed to avoid metastability if the physical pin changes value near
the edge of the internal clock, but it also introduces a delay.
the synchronization when reading an externally applied pin value. The maximum and minimum
propagation delays are denoted t
Figure 24. Synchronization when Reading an Externally Applied Pin Value
Consider the clock period starting shortly after the first falling edge of the system clock. The latch
is closed when the clock is low, and goes transparent when the clock is high, as indicated by the
shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock
goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As
indicated by the two arrows t
between ½ and 1½ system clock period depending upon the time of assertion.
DDxn
0
0
0
1
1
INSTRUCTIONS
SYSTEM CLK
SYNC LATCH
summarizes the control signals for the pin value.
PORTxn
0
1
1
0
1
PINxn
r17
(in SFIOR)
PUD
X
0
1
X
X
pd,max
Figure
XXX
Output
Output
pd,max
Input
Input
Input
and t
I/O
23, the PINxn Register bit and the preceding latch consti-
and t
pd,min
Pull-up
Yes
t
pd,min
No
No
No
No
pd, max
, a single signal transition on the pin will be delayed
0x00
respectively.
XXX
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
t
pd, min
Figure 24
in r17, PINx
shows a timing diagram of
ATmega32(L)
0xFF
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