ATMEGA324P-A15MZ Atmel, ATMEGA324P-A15MZ Datasheet - Page 77

• Manufacturer Part Number: ATMEGA324P-A15MZ
• Description: MCU AVR 32KB FLASH 15MHZ 44-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 1K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Timer/Counter
Timing Diagrams
2503N–AVR–06/08
between OCR0 and TCNT0 when the counter increments, and setting (or clearing) the OC0
Register at compare match between OCR0 and TCNT0 when the counter decrements. The
PWM frequency for the output when using phase correct PWM can be calculated by the follow-
ing equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0 Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-
put will be continuously low and if set equal to MAX the output will be continuously high for non-
inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
is no Compare Match. The point of this transition is to guarantee symmetry around BOTTOM.
There are two cases that give a transition without Compare Match:
•
•
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 34. Timer/Counter Timing Diagram, no Prescaling
Figure 35
OCR0A changes its value from MAX, like in
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
The timer starts counting from a value higher than the one in OCR0A, and for that reason
misses the Compare Match and hence the OCn change that would have happened on the
way up.
TCNTn
(clk
TOVn
clk
clk
I/O
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
Figure 34
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 33
f
OCnPCPWM
OCn has a transition from high to low even though there
MAX
Figure
=
----------------- -
N 510
f
clk_I/O
⋅
33. When the OCR0A value is MAX the
BOTTOM
T0
ATmega32(L)
) is therefore shown as a
BOTTOM + 1
77