ATMEGA324P-A15MZ Atmel, ATMEGA324P-A15MZ Datasheet - Page 291

• Manufacturer Part Number: ATMEGA324P-A15MZ
• Description: MCU AVR 32KB FLASH 15MHZ 44-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 1K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

SPI Timing
Characteristics
2503N–AVR–06/08
Figure 145. Two-wire Serial Bus Timing
See
Table 120. SPI Timing Parameters
10
11
12
13
14
15
16
17
18
1
2
3
4
5
6
7
8
9
Figure 146
SCL
SDA
5. This requirement applies to all ATmega32 Two-wire Serial Interface operation. Other devices
6. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/f
7. The actual low period generated by the ATmega32 Two-wire Serial Interface is (1/f
SS high to tri-state
t
SU;STA
SCK to out high
connected to the Two-wire Serial Bus need only obey the general f
thus f
100 kHz.
thus the low time requirement will not be strictly met for f
ATmega32 devices connected to the bus may communicate at full speed (400 kHz) with other
ATmega32 devices, as well as any other device with a proper t
SCK to SS high
SS low to SCK
SCK high/low
Rise/Fall time
SCK high/low
Rise/Fall time
SS low to out
Description
SCK period
Out to SCK
SCK period
SCK to out
SCK to out
Setup
Setup
and
Hold
Hold
CK
must be greater than 6 MHz for the low time requirement to be strictly met at f
Figure 147
t
HD;STA
t
t
of
LOW
for details.
Master
Master
Master
Master
Master
Master
Master
Master
Mode
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Salve
Slave
t
HIGH
t
HD;DAT
4 • t
2 • t
2 • t
Min
10
20
t
ck
ck
ck
ck
t
LOW
t
50% duty cycle
SU;DAT
See
0.5 • t
Table 58
Typ
3.6
10
10
10
10
15
15
10
SCL
SCK
> 308 kHz when f
LOW
ATmega32(L)
SCL
acceptance margin.
Max
1.6
requirement.
t
SU;STO
t
r
CK
ns
µs
ns
= 8 MHz. Still,
SCL
SCL
t
BUF
- 2/f
- 2/f
SCL
291
CK
CK
),
),
=