ATMEGA324P-A15MZ Atmel, ATMEGA324P-A15MZ Datasheet - Page 42

• Manufacturer Part Number: ATMEGA324P-A15MZ
• Description: MCU AVR 32KB FLASH 15MHZ 44-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 1K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Watchdog Timer
Control Register –
WDTCR
42
ATmega32(L)
• Bits 7..5 – Res: Reserved Bits
These bits are reserved bits in the ATmega32 and will always read as zero.
• Bit 4 – WDTOE: Watchdog Turn-off Enable
This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not
be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the
description of the WDE bit for a Watchdog disable procedure.
• Bit 3 – WDE: Watchdog Enable
When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written
to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDTOE
bit has logic level one. To disable an enabled Watchdog Timer, the following procedure must be
followed:
1. In the same operation, write a logic one to WDTOE and WDE. A logic one must be writ-
2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.
• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1, and 0
The WDP2, WDP1, and WDP0 bits determine the Watchdog Timer prescaling when the Watch-
dog Timer is enabled. The different prescaling values and their corresponding Timeout Periods
are shown in
Table 17. Watchdog Timer Prescale Select
Bit
Read/Write
Initial Value
WDP2
0
0
0
0
1
1
1
1
ten to WDE even though it is set to one before the disable operation starts.
WDP1
0
0
1
1
0
0
1
1
Table
R
7
–
0
WDP0
17.
0
1
0
1
0
1
0
1
R
6
–
0
1,024K (1,048,576)
2,048K (2,097,152)
Oscillator Cycles
Number of WDT
128K (131,072)
256K (262,144)
512K (524,288)
16K (16,384)
32K (32,768)
64K (65,536)
R
5
–
0
WDTOE
R/W
4
0
WDE
R/W
3
0
Typical Time-out
at V
WDP2
17.1 ms
34.3 ms
68.5 ms
R/W
0.14 s
0.27 s
0.55 s
CC
1.1 s
2.2 s
2
0
= 3.0V
WDP1
R/W
1
0
Typical Time-out
WDP0
at V
R/W
0
0
16.3 ms
32.5 ms
65 ms
0.13 s
0.26 s
0.52 s
CC
1.0 s
2.1 s
= 5.0V
WDTCR
2503N–AVR–06/08