ATMEGA324P-A15MZ Atmel, ATMEGA324P-A15MZ Datasheet - Page 80

• Manufacturer Part Number: ATMEGA324P-A15MZ
• Description: MCU AVR 32KB FLASH 15MHZ 44-VQFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA324P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 1K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Program Memory Size: 32KB (32K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-bit
Timer/Counter
Register
Description
Timer/Counter Control
Register – TCCR0
80
ATmega32(L)
• Bit 7 – FOC0: Force Output Compare
The FOC0 bit is only active when the WGM00 bit specifies a non-PWM mode. However, for
ensuring compatibility with future devices, this bit must be set to zero when TCCR0 is written
when operating in PWM mode. When writing a logical one to the FOC0 bit, an immediate com-
pare match is forced on the Waveform Generation unit. The OC0 output is changed according to
its COM01:0 bits setting. Note that the FOC0 bit is implemented as a strobe. Therefore it is the
value present in the COM01:0 bits that determines the effect of the forced compare.
A FOC0 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0 as TOP.
The FOC0 bit is always read as zero.
• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of Waveform Generation to be used. Modes of operation sup-
ported by the Timer/Counter unit are: Normal mode, Clear Timer on Compare Match (CTC)
mode, and two types of Pulse Width Modulation (PWM) modes. See
Operation” on page
Table 38. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM01:0: Compare Match Output Mode
These bits control the Output Compare pin (OC0) behavior. If one or both of the COM01:0 bits
are set, the OC0 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to the OC0 pin must be
set in order to enable the output driver.
Bit
Read/Write
Initial Value
Mode
0
1
2
3
1. The CTC0 and PWM0 bit definition names are now obsolete. Use the WGM01:0 definitions.
WGM01
(CTC0)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
FOC0
W
7
0
73.
WGM00
(PWM0)
WGM00
R/W
0
1
0
1
6
0
COM01
Timer/Counter Mode
of Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
R/W
5
0
COM00
R/W
4
0
WGM01
R/W
3
0
TOP
0xFF
0xFF
OCR0
0xFF
(1)
CS02
R/W
2
0
Update of
OCR0
Immediate
TOP
Immediate
BOTTOM
CS01
R/W
1
0
Table 38
CS00
R/W
0
0
TOV0 Flag
Set-on
MAX
BOTTOM
MAX
MAX
TCCR0
and
2503N–AVR–06/08
“Modes of