D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 142
D13007VX13V
Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13007VX13V
Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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6. Bus Controller
6.2
6.2.1
ABWCR is an 8-bit readable/writable register that selects 8-bit or 16-bit access for each area.
Bit
When ABWCR contains H'FF (selecting 8-bit access for all areas), the chip operates in 8-bit bus
mode: the upper data bus (D
bit is cleared to 0 in ABWCR, the chip operates in 16-bit bus mode with a 16-bit data bus (D
D
modes 2 and 4, ABWCR is initialized to H'00 by a reset and in hardware standby mode. It is not
initialized in software standby mode.
Bits 7 to 0⎯Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select 8-bit access
or 16-bit access for the corresponding areas.
Bits 7 to 0
ABW7 to ABW0
0
1
ABWCR specifies the data bus width of external memory areas. The data bus width of on-chip
memory and registers is fixed, and does not depend on ABWCR settings.
Rev.5.00 Sep. 12, 2007 Page 112 of 764
REJ09B0396-0500
Modes
1 and 3
Modes
2 and 4
0
). In modes 1 and 3, ABWCR is initialized to H'FF by a reset and in hardware standby mode. In
Register Descriptions
Bus Width Control Register (ABWCR)
Initial value
Read/Write
Initial value
Read/Write
Description
Areas 7 to 0 are 16-bit access areas
Areas 7 to 0 are 8-bit access areas
ABW7
R/W
R/W
7
1
0
15
to D
ABW6
R/W
R/W
8
6
1
0
) is valid, and port 4 is an input/output port. When at least one
ABW5
R/W
R/W
5
1
0
ABW4
R/W
R/W
4
1
0
ABW3
R/W
R/W
3
1
0
ABW2
R/W
R/W
2
1
0
ABW1
R/W
R/W
1
1
0
ABW0
R/W
R/W
15
0
1
0
to
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