D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 197

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

• Figure 6.31 shows typical interconnections when using two 4-Mbit DRAMs, and the
Figure 6.31 Interconnections and Address Map for 2-CAS 4-Mbit DRAMs with × 16-Bit
corresponding address map. The DRAMs used in this example are of the 9-bit row address ×
9-bit column address type. In this example, upper address decoding allows multiple DRAMs to
be connected to a single area. The RFSH pin is used in this case, since both DRAMs must be
refreshed simultaneously. However, note that RAS down mode cannot be used in this
interconnection example.
H8/3006 and H8/3007
Area 2
PB4 (UCAS)
CS2 (RAS2)
PB5 (LCAS)
RD (WE)
D15-D0
RFSH
A9-A1
A19
H'400000
H'47FFFE
H'480000
H'4FFFFE
H'500000
H'5FFFFE
(a) Interconnections (example)
15
(UCAS)
PB4
(b) Address map
16-Mbyte mode
Organization
DRAM (No.1)
DRAM (No.2)
Not used
8
7
(LCAS)
PB5
0
CS2 (RAS2)
Rev.5.00 Sep. 12, 2007 Page 167 of 764
9-bit row address × 9-bit column address
RAS
UCAS
LCAS
WE
D15-D0
RAS
UCAS
LCAS
WE
D15-D0
A8-A0
A8-A0
2-CAS 4-Mbit DRAM
× 16-bit organization
OE
OE
No.1
No.2
REJ09B0396-0500
6. Bus Controller