D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 474

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

13. Serial Communication Interface
For smart card interface (SMIF bit in SCMR set to 1): Indicates the status of the error signal
sent back from the receiving side during transmission. Framing errors are not detected in smart
card interface mode.
Bit 4
ERS
0
1
Note:
Bit 3⎯Parity Error (PER): Indicates that data reception ended abnormally due to a parity error
in asynchronous mode.
Bit 3
PER
0
1
Notes: 1. Clearing the RE bit to 0 in SCR does not affect the PER flag, which retains its previous
Bit 2⎯Transmit End (TEND): The function of this bit differs for the normal serial
communication interface and for the smart card interface. Its function is switched with the SMIF
bit in SCMR.
Rev.5.00 Sep. 12, 2007 Page 444 of 764
REJ09B0396-0500
* Clearing the TE bit to 0 in SCR does not affect the ERS flag, which retains its previous
2. When a parity error occurs the SCI transfers the receive data into RDR but does not set
value.
value.
the RDRF flag. Serial receiving cannot continue while the PER flag is set to 1. In
synchronous mode, serial transmitting is also disabled.
Description
Normal reception, no error signal*
[Clearing conditions]
•
•
An error signal has been sent from the receiving side indicating detection of a
parity error
[Setting condition]
The error signal is low when sampled
Description
Receiving is in progress or has ended normally*
[Clearing conditions]
•
•
A receive parity error occurred*
[Setting condition]
The number of 1s in receive data, including the parity bit, does not match the
even or odd parity setting of O/E in SMR
The chip is reset or enters standby mode
Read ERS when ERS = 1, then write 0 in ERS
The chip is reset or enters standby mode
Read PER when PER = 1, then write 0 in PER
2
1
(Initial value)
(Initial value)