D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 577

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

18.1
The H8/3006 and H8/3007 have a built-in clock pulse generator (CPG) that generates the system
clock (φ) and other internal clock signals (φ/2 to φ/4096). After duty adjustment, a frequency
divider divides the clock frequency to generate the system clock (φ). The system clock is output at
the φ pin*
supporting modules. Frequency division ratios of 1/1, 1/2, 1/4, and 1/8 can be selected for the
frequency divider by settings in a division control register (DIVCR)*
chip is reduced in almost direct proportion to the frequency division ratio.
Notes: 1. Usage of the φ pin differs depending on the chip operating mode and the PSTOP bit
18.1.1
Figure 18.1 shows a block diagram of the clock pulse generator.
2. The division ratio of the frequency divider can be changed dynamically during
Overview
Block Diagram
1
setting in the module standby control register (MSTCR). For details, see section 19.7,
System Clock Output Disabling Function.
operation. The clock output at the φ pin also changes when the division ratio is
changed. The frequency output at the φ pin is shown below.
where, EXTAL:Frequency of crystal resonator or external clock signal
and furnished as a master clock to prescalers that supply clock signals to the on-chip
XTAL
EXTAL
φ = EXTAL × n
n:
Figure 18.1 Block Diagram of Clock Pulse Generator
Section 18 Clock Pulse Generator
Frequency division ratio (n = 1/1, 1/2, 1/4, or 1/8)
Oscillator
adjustment
circuit
Duty
Frequency
Data bus
Rev.5.00 Sep. 12, 2007 Page 547 of 764
Division
register
control
divider
φ
2
. Power consumption in the
18. Clock Pulse Generator
φ/2 to φ/4096
Prescalers
CPG
REJ09B0396-0500