D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 222

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

7. DMA Controller
7.2.1
A memory address register (MAR) is a 32-bit readable/writable register that specifies a source or
destination address. The transfer direction is determined automatically from the activation source.
An MAR consists of four 8-bit registers designated MARR, MARE, MARH, and MARL. All bits
of MARR are reserved; they cannot be modified and are always read as 1.
An MAR functions as a source or destination address register depending on how the DMAC is
activated: as a destination address register if activation is by a receive-data-full interrupt from the
serial communication interface (SCI) (channel 0) or by a conversion-end interrupt from the A/D
converter, and as a source address register otherwise.
The MAR value is incremented or decremented each time one byte or word is transferred,
automatically updating the source or destination memory address. For details, see section 7.3.4,
Data Transfer Control Registers (DTCR).
The MARs are not initialized by a reset or in standby mode.
7.2.2
An I/O address register (IOAR) is an 8-bit readable/writable register that specifies a source or
destination address. The IOAR value is the lower 8 bits of the address. The upper 16 address bits
are all 1 (H'FFFF).
Bit
Initial value
Read/Write
An IOAR functions as a source or destination address register depending on how the DMAC is
activated: as a source address register if activation is by a receive-data-full interrupt from the SCI
Rev.5.00 Sep. 12, 2007 Page 192 of 764
REJ09B0396-0500
Bit
Initial value
Read/Write
31
⎯
Memory Address Registers (MAR)
I/O Address Registers (IOAR)
1
30
⎯
1
29
⎯
1
R/W
MARR
28
⎯
1
7
27
⎯
1
26
⎯
1
25
⎯
1
R/W
24
⎯
6
1
R/W
23
R/W
22
R/W
21
R/W
5
Source or destination address
R/W
MARE
20
Source or destination address
R/W
19
R/W
18
Undetermined
R/W
R/W
17
4
R/W
16
R/W
15
R/W
14
R/W
3
R/W
13
Undetermined
R/W
MARH
12
R/W
11
R/W
R/W
10
2
R/W
9
R/W
8
R/W
7
R/W
R/W
1
6
R/W
5
R/W
MARL
4
R/W
R/W
3
0
R/W
2
R/W
1
R/W
0