D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 495

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

In receiving, the SCI operates as follows:
• The SCI monitors the communication line. When it detects a start bit (0 bit), the SCI
• Receive data is stored in RSR in order from LSB to MSB.
• The parity bit and stop bit are received.
Note: * When a receive error occurs, further receiving is disabled. In receiving, the RDRF flag
• When the RDRF flag is set to 1, if the RIE bit is set to 1 in SCR, a receive-data-full interrupt
Table 13.11 Receive Error Conditions
Receive Error Abbreviation Condition
Overrun error ORER
Framing error FER
Parity error
synchronizes internally and starts receiving.
After receiving these bits, the SCI carries out the following checks:
⎯ Parity check: The number of 1s in the receive data must match the even or odd parity
⎯ Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first is
⎯ Status check: The RDRF flag must be 0, indicating that the receive data can be transferred
If these all checks pass, the RDRF flag is set to 1 and the received data is stored in RDR. If one
of the checks fails (receive error*), the SCI operates as shown in table 13.11.
(RXI) is requested. If the ORER, PER, or FER flag is set to 1 and the RIE bit in SCR is also
set to 1, a receive-error interrupt (ERI) is requested.
setting of in the O/E bit in SMR.
checked.
from RSR into RDR.
is not set to 1. Be sure to clear the error flags to 0.
PER
Receiving of next data ends while
RDRF flag is still set to 1 in SSR
Stop bit is 0
Parity of received data differs from
even/odd parity setting in SMR
Rev.5.00 Sep. 12, 2007 Page 465 of 764
13. Serial Communication Interface
Data Transfer
Receive data is not transferred
from RSR to RDR
Receive data is transferred from
RSR to RDR
Receive data is transferred from
RSR to RDR
REJ09B0396-0500