D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 192

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
Use the RLW bit in DRCRB to adjust the RAS signal width. A single refresh wait state (T
be inserted between the T
The RLW bit setting is valid only for CBR refresh cycles, and does not affect DRAM read/write
cycles. The number of states in the CBR refresh cycle is not affected by the settings in ASTCR,
WCRH, or WCRL, or by the state of the WAIT pin.
Figure 6.27 shows the timing when the TPC bit and RLW bit are both set to 1.
DRAM must be refreshed immediately after powering on in order to stabilize its internal state.
When using the H8/3006 and H8/3007 CAS-before-RAS refresh function, therefore, a DRAM
stabilization period should be provided by means of interrupts by another timer module, or by
counting the number of times bit 7 (CMF) of RTMCSR is set, for instance, immediately after bits
DRAS2 to DRAS0 have been set in DRCRA.
Rev.5.00 Sep. 12, 2007 Page 162 of 764
REJ09B0396-0500
(UCAS/LCAS)
Address bus
PB4/PB5
CS
RD(WE)
RFSH
n
Figure 6.27 CBR Refresh Timing (CSEL = 0, TPC = 1, RLW = 1)
(RAS)
AS
φ
R1
T
state and T
Rp1
R2
state by setting the RLW bit to 1.
T
RP2
Area 2 start address
High
High
T
R1
T
RW
T
R2
RW
) can