D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 163

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Table 6.3
ABWCR ASTCR WCRH/WCRL
ABWn
0
1
6.3.3
The H8/3006 and H8/3007 memory interfaces comprise a basic bus interface that allows direct
connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of
DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can
be selected independently for each area.
An area for which the basic bus interface is designated functions as normal space, an area for
which the DRAM interface is designated functions as DRAM space, and area 0 for which the burst
ROM interface is designated functions as burst ROM space.
6.3.4
For each of areas 0 to 7, the H8/3006 and H8/3007 can output a chip select signal (CS
goes low when the corresponding area is selected. Figure 6.4 shows the output timing of a CSn
signal.
Output of CS
(DDR) of the corresponding port.
A reset leaves pin CS
select signals CS
I/O Ports.
ASTn
0
1
0
1
Memory Interfaces
Chip Select Signals
Bus Specifications for Each Area (Basic Bus Interface)
0
to CS
1
to CS
Wn1
⎯
0
1
⎯
0
1
3
0
: Output of CS
in the output state and pins CS
3
, the corresponding DDR bits must be set to 1. For details, see section 8,
Wn0
⎯
0
1
0
1
⎯
0
1
0
1
0
to CS
Bus Specifications (Basic Bus Interface)
Bus Width
16
8
3
is enabled or disabled in the data direction register
1
Access States
2
3
2
3
to CS
Rev.5.00 Sep. 12, 2007 Page 133 of 764
3
in the input state. To output chip
Program Wait States
0
0
1
2
3
0
0
1
2
3
REJ09B0396-0500
6. Bus Controller
0
to CS
7
) that