D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 164

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
Output of CS
register (CSCR). A reset leaves pins CS
to CS
When the on-chip RAM and on-chip registers are accessed, CS
signals are decoded from the address signals. They can be used as chip select signals for SRAM
and other devices.
6.4
6.4.1
The basic bus interface enables direct connection of ROM, SRAM, and so on.
The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL
(see table 6.3).
6.4.2
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external space, controls whether the
upper data bus (D
for the area being accessed (8-bit access area or 16-bit access area) and the data size.
Rev.5.00 Sep. 12, 2007 Page 134 of 764
REJ09B0396-0500
7
, the corresponding CSCR bits must be set to 1. For details, see section 8, I/O Ports.
Basic Bus Interface
Overview
Data Size and Data Alignment
4
to CS
15
Address bus
to D
7
: Output of CS
CS
Figure 6.4 CSn Signal Output Timing (n = 0 to 7)
φ
8
) or lower data bus (D
n
4
to CS
4
to CS
7
is enabled or disabled in the chip select control
External address in area n
7
7
in the input state. To output chip select signals CS
to D
0
) is used according to the bus specifications
0
to CS
7
remain high. The CS
n
4