D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 156

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
Bit 4⎯Refresh Cycle Enable (RCYCE): CAS-before-RAS enables or disables refresh cycle
insertion. When none of areas 2 to 5 has been designated as DRAM space, refresh cycles are not
inserted regardless of the setting of this bit.
Bit 4
RCYCE
0
1
Bit 3⎯Reserved: This bit cannot be modified and is always read as 1.
Bit 2⎯TP Cycle Control (TPC): Selects whether a 1-state or two-state precharge cycle (Tp) is to
be used for DRAM read/write cycles and CAS-before-RAS refresh cycles. The setting of this bit
does not affect the self-refresh function.
Bit 2
TPC
0
1
Bit 1⎯RAS-CAS Wait (RCW): Controls wait state (Trw) insertion between T
read/write cycles. The setting of this bit does not affect refresh cycles.
Bit 1
RCW
0
1
Bit 0⎯Refresh Cycle Wait Control (RLW): Controls wait state (T
RAS refresh cycles. The setting of this bit does not affect DRAM read/write cycles.
Bit 0
RLW
0
1
Rev.5.00 Sep. 12, 2007 Page 126 of 764
REJ09B0396-0500
Description
Refresh cycles disabled
DRAM refresh cycles enabled
Description
1-state precharge cycle inserted
2-state precharge cycle inserted
Description
Wait state (Trw) insertion disabled
One wait state (Trw) inserted
Description
Wait state (T
One wait state (T
RW
) insertion disabled
RW
) inserted
RW
) insertion for CAS-before-
r
and T
(Initial value)
(Initial value)
(Initial value)
(Initial value)
c1
in DRAM