D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 21

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

Section 7 DMA Controller
7.1
7.2
7.3
7.4
7.5
7.6
6.11.2 BREQ Pin Input Timing ...................................................................................... 186
Overview........................................................................................................................... 187
7.1.1
7.1.2
7.1.3
7.1.4
7.1.5
Register Descriptions (1) (Short Address Mode) .............................................................. 191
7.2.1
7.2.2
7.2.3
7.2.4
Register Descriptions (2) (Full Address Mode) ................................................................ 198
7.3.1
7.3.2
7.3.3
7.3.4
Operation........................................................................................................................... 207
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
7.4.10 External Bus Requests, DRAM Interface, and DMAC........................................ 234
7.4.11 NMI Interrupts and DMAC.................................................................................. 235
7.4.12 Aborting a DMAC Transfer................................................................................. 236
7.4.13 Exiting Full Address Mode .................................................................................. 237
7.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode.......................... 238
Interrupts ........................................................................................................................... 238
Usage Notes ...................................................................................................................... 239
7.6.1
7.6.2
7.6.3
7.6.4
Features................................................................................................................ 187
Block Diagram ..................................................................................................... 188
Functional Overview............................................................................................ 188
Pin Configuration................................................................................................. 190
Register Configuration......................................................................................... 190
Memory Address Registers (MAR) ..................................................................... 192
I/O Address Registers (IOAR) ............................................................................. 192
Execute Transfer Count Registers (ETCR) .......................................................... 193
Data Transfer Control Registers (DTCR) ............................................................ 195
Memory Address Registers (MAR) ..................................................................... 198
I/O Address Registers (IOAR) ............................................................................. 198
Execute Transfer Count Registers (ETCR) .......................................................... 199
Data Transfer Control Registers (DTCR) ............................................................ 201
Overview.............................................................................................................. 207
I/O Mode.............................................................................................................. 209
Idle Mode............................................................................................................. 211
Repeat Mode ........................................................................................................ 214
Normal Mode....................................................................................................... 218
Block Transfer Mode ........................................................................................... 221
DMAC Activation................................................................................................ 226
DMAC Bus Cycle ................................................................................................ 227
Multiple-Channel Operation ................................................................................ 233
Note on Word Data Transfer................................................................................ 239
DMAC Self-Access ............................................................................................. 239
Longword Access to Memory Address Registers ................................................ 240
Note on Full Address Mode Setup ....................................................................... 240
................................................................................................ 187
Rev.5.00 Sep. 12, 2007 Page xix of xxviii
REJ09B0396-0500