D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 143

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.2.2
ASTCR is an 8-bit readable/writable register that selects whether each area is accessed in two
states or three states.
Bit
Initial value
Read/Write
ASTCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 7 to 0⎯Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the
corresponding area is accessed in two or three states.
Bits 7 to 0
AST7 to AST0
0
1
ASTCR specifies the number of states in which external areas are accessed. On-chip memory and
registers are accessed in a fixed number of states that does not depend on ASTCR settings.
When the corresponding area is designated as DRAM space by bits DRAS2 to DRAS0 in DRAM
control register A (DRCRA), the number of access states does not depend on the AST bit setting.
When an AST bit is cleared to 0, programmable wait insertion is not performed.
6.2.3
WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait
states for each area.
On-chip memory and registers are accessed in a fixed number of states that does not depend on
WCRH/WCRL settings.
WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not
initialized in software standby mode.
Access State Control Register (ASTCR)
Wait Control Registers H and L (WCRH, WCRL)
AST7
R/W
Description
Areas 7 to 0 are accessed in two states
Areas 7 to 0 are accessed in three states
7
1
AST6
R/W
Bits selecting number of states for access to each area
6
1
AST5
R/W
5
1
AST4
R/W
4
1
Rev.5.00 Sep. 12, 2007 Page 113 of 764
AST3
R/W
3
1
AST2
R/W
2
1
REJ09B0396-0500
AST1
6. Bus Controller
R/W
1
1
(Initial value)
AST0
R/W
0
1