D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 182

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6. Bus Controller
6.5.8
In a DRAM access cycle, wait states can be inserted (1) between the T
between the T
Insertion of T
by setting the RCW bit to 1 in DRCRB.
Insertion of T
area designated as DRAM space is set to 1, from 0 to 3 T
state and T
Figure 6.18 shows an example of the timing for wait state insertion.
The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh
cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin.
Rev.5.00 Sep. 12, 2007 Page 152 of 764
REJ09B0396-0500
Wait Control
c2
Read access
Write access
state by means of settings in WCRH and WCRL.
c1
rw
w
Figure 6.18 Example of Wait State Insertion Timing (CSEL = 0)
state and T
Wait State(s) between T
Wait State between T
(UCAS /LCAS)
(UCAS /LCAS)
Note: n = 2 to 5
c2
PB4 /PB5
PB4 /PB5
state.
CSn(RAS)
RD(WE)
D
D
A
RD(WE)
23
15
15
φ
to A
to D
to D
AS
0
0
0
r
and T
c1
and T
T
p
c1
: One T
c2
Tr
: When the bit in ASTCR corresponding to an
Row
Trw
rw
w
state can be inserted between T
states can be inserted between the T
High
High
T
c1
Column
Tw
Write data
r
state and T
Tw
Read data
T
c2
c1
state, and (2)
r
and T
c1
c1