D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 506
D13007VX13V
Manufacturer Part Number
D13007VX13V
Description
MCU 3V 0K 100-TQFP
Manufacturer
Renesas Electronics America
Series
H8® H8/300Hr
Specifications of D13007VX13V
Core Processor
H8/300H
Core Size
16-Bit
Speed
13MHz
Connectivity
SCI, SmartCard
Peripherals
DMA, PWM, WDT
Number Of I /o
35
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 75°C
Package / Case
100-TQFP, 100-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
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13. Serial Communication Interface
• After loading the data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
• The SCI checks the TDRE flag when it outputs the MSB (bit 7). If the TDRE flag is 0, the SCI
• After the end of serial transmission, the SCK pin is held in a constant state.
Figure 13.17 shows an example of SCI transmit operation.
Rev.5.00 Sep. 12, 2007 Page 476 of 764
REJ09B0396-0500
Serial clock
Serial data
TDRE
TEND
transmitting. If the TIE bit is set to 1 in SCR, the SCI requests a transmit-data-empty interrupt
(TXI) at this time.
If clock output is selected, the SCI outputs eight serial clock pulses. If an external clock source
is selected, the SCI outputs data in synchronization with the input clock. Data is output from
the TxD pin n order from LSB (bit 0) to MSB (bit 7).
loads data from TDR into TSR and begins serial transmission of the next frame. If the TDRE
flag is 1, the SCI sets the TEND flag to 1 in SSR, and after transmitting the MSB, holds the
TxD pin in the MSB state. If the TEIE bit is set to 1 in SCR, a transmit-end interrupt (TEI) is
requested at this time
TXI interrupt
request
Figure 13.17 Example of SCI Transmit Operation
TXI interrupt handler
writes data in TDR
and clears TDRE
flag to 0
Bit 0
Transmit direction
Bit 1
1 frame
TXI interrupt
request
Bit 7
Bit 0
Bit 1
Bit 6
TEI interrupt
request
Bit 7
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