D13007VX13V Renesas Electronics America, D13007VX13V Datasheet - Page 177

• Manufacturer Part Number: D13007VX13V
• Description: MCU 3V 0K 100-TQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Hr

Specifications of D13007VX13V

• Core Processor: H8/300H
• Core Size: 16-Bit
• Speed: 13MHz
• Connectivity: SCI, SmartCard
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 35
• Program Memory Type: ROMless
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

6.5
6.5.1
The H8/3006 and H8/3007 are provided with a DRAM interface with functions for DRAM control
signal (RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct
connection of DRAM. In the expanded modes, external address space areas 2 to 5 can be
designated as DRAM space accessed via the DRAM interface. A data bus width of 8 or 16 bits can
be selected for DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is
selected, CAS is used for byte access control. In the case of × 16-bit organization DRAM,
therefore, the 2-CAS type can be connected. A fast page mode is supported in addition to the
normal read and write access modes.
6.5.2
Designation of areas 2 to 5 as DRAM space, and selection of the RAS output pin for each area
designated as DRAM space, is performed by setting bits DRAS2 to DRAS0 in DRCRA. Table 6.5
shows the correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM
space and RAS output pin.
When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than
000 must not be performed.
Table 6.5
DRAS2 DRAS1 DRAS0 Area 5
0
1
Note:
* A single CS
0
1
0
1
DRAM Interface
Overview
DRAM Space and RAS Output Pin Settings
CS
Settings of Bits DRAS2 to DRAS0 and Corresponding DRAM Space
(RAS Output Pin)
n
pins can be used as input/output ports.
0
1
0
1
0
1
0
1
n
pin serves as a common RAS output pin for a number of areas. Unused
Normal space
Normal space
Normal space
Normal space
Normal space
DRAM space
(CS
5
)
DRAM space (CS
Area 4
Normal space
Normal space
Normal space
Normal space
DRAM space
(CS
DRAM space
(CS
4
4
)
)
4
)*
DRAM space (CS
Rev.5.00 Sep. 12, 2007 Page 147 of 764
Area 3
Normal space
Normal space
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
3
3
3
)
)
)
2
DRAM space (CS
DRAM space (CS
)*
REJ09B0396-0500
6. Bus Controller
Area 2
Normal space
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
DRAM space
(CS
2
2
2
2
)
)
)
)
2
2
)*
)*