R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 103

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Notes: 1. For details on instruction fetch mode, see section 2.3, Instruction Fetch.
Bit
10
9
8
7 to 2
1
0
2. The initial value depends on the LSI initiation mode.
Bit Name

EXPE
RAME

DTCMD

EXPE = 1 because operating modes 4, 5, and 6 are external extended modes.
Initial
Value
Undefined
Undefined
1
All 0
1
1
*
*
2
2
R/W
R
R/W
R/W
R/W
R/W
R/W
Descriptions
Reserved
This bit is fixed at 1 in on-chip ROM enabled mode, and
0 in on-chip ROM disabled mode. This bit cannot be
changed.
External Bus Mode Enable
Selects external bus mode. In external extended mode,
this bit is fixed at 1 and cannot be changed. In single-
chip mode, the initial value of this bit is 0, and can be
read from or written to.
When writing 0 to this bit after reading EXPE = 1, an
external bus cycle should not be executed.
The external bus cycle may be carried out in parallel
with the internal bus cycle depending on the setting of
the write data buffer function.
0: External bus disabled
1: External bus enabled
RAM Enable
Enables or disables the on-chip RAM. This bit is
initialized when the reset state is released. Do not write
0 during access to the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
Reserved
These bits are always read as 0. The write value should
always be 0.
DTC Mode Select
Selects DTC operating mode.
0: DTC is in full-address mode
1: DTC is in short address mode
Reserved
This bit is always read as 1. The write value should
always be 1.
Rev. 2.00 Sep. 16, 2009 Page 73 of 1036
Section 3 MCU Operating Modes
REJ09B0414-0200