R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 343

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
9.5.9
Figure 9.23 shows an examples of signal timing of a basic bus cycle. In figure 9.23, data is
transferred in words from the 16-bit 2-state access space to the 8-bit 3-state access space. When
the bus mastership is passed from the DMAC to the CPU, data is read from the source address and
it is written to the destination address. The bus is not released between the read and write cycles
by other bus requests. DMAC bus cycles follows the bus controller settings.
Address bus
RD
LHWR
LLWR
DMA Basic Bus Cycle
High
CPU cycle
Figure 9.23 Example of Bus Timing of DMA Transfer
Source address
T
1
T
2
T
1
DMAC cycle (one word transfer)
T
2
Destination address
T
3
Rev. 2.00 Sep. 16, 2009 Page 313 of 1036
T
1
Section 9 DMA Controller (DMAC)
T
2
T
3
REJ09B0414-0200
CPU cycle

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