R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 640
R5F61662N50FPV
Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet
1.R0K561622S000BE.pdf
(1070 pages)
Specifications of R5F61662N50FPV
Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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Section 16 Serial Communication Interface (SCI)
Note:
16.3.6
SCR is a register that enables/disables the following SCI transfer operations and interrupt requests,
and selects the transfer clock source. For details on interrupt requests, see section 16.8, Interrupt
Sources. Some bits in SCR have different functions in normal mode and smart card interface
mode.
• When SMIF in SCMR = 0
• When SMIF in SCMR = 1
Rev. 2.00 Sep. 16, 2009 Page 610 of 1036
REJ09B0414-0200
Bit
1
0
Bit
Bit Name
Initial Value
R/W
Bit
Bit Name
Initial Value
R/W
etu (Elementary Time Unit): 1-bit transfer time
Serial Control Register (SCR)
Bit Name
CKS1
CKS0
R/W
R/W
TIE
TIE
7
0
7
0
Initial
Value
0
0
R/W
R/W
RIE
RIE
6
0
6
0
R/W
R/W
R/W
R/W
R/W
TE
TE
5
0
5
0
Description
Clock Select 1,0
These bits select the clock source for the baud rate
generator.
00: Pφ clock (n = 0)
01: Pφ/4 clock (n = 1)
10: Pφ/16 clock (n = 2)
11: Pφ/64 clock (n = 3)
For the relation between the settings of these bits and
the baud rate, see section 16.3.9, Bit Rate Register
(BRR). n is the decimal display of the value of n in BRR
(see section 16.3.9, Bit Rate Register (BRR)).
R/W
R/W
RE
RE
4
0
4
0
MPIE
MPIE
R/W
R/W
3
0
3
0
TEIE
TEIE
R/W
R/W
2
0
2
0
CKE1
CKE1
R/W
R/W
1
0
1
0
CKE0
CKE0
R/W
R/W
0
0
0
0
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