R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 23

MCU 24KB FLASH 384K 144-LQFP

R5F61662N50FPV

Manufacturer Part Number
R5F61662N50FPV
Description
MCU 24KB FLASH 384K 144-LQFP
Manufacturer
Renesas Electronics America
Series
H8® H8SX/1600r
Datasheet

Specifications of R5F61662N50FPV

Core Processor
H8SX
Core Size
16/32-Bit
Speed
50MHz
Connectivity
EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
Peripherals
DMA, LVD, POR, PWM, WDT
Number Of I /o
92
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
40K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 2x8b
Oscillator Type
External
Operating Temperature
-20°C ~ 75°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F61662N50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
16.4
16.5
16.6
16.7
16.8
16.9
16.3.10 Serial Extended Mode Register_2 (SEMR_2) .................................................. 635
Operation in Asynchronous Mode .................................................................................... 637
16.4.1
16.4.2
16.4.3
16.4.4
16.4.5
16.4.6
Multiprocessor Communication Function......................................................................... 648
16.5.1
16.5.2
Operation in Clocked Synchronous Mode ........................................................................ 654
16.6.1
16.6.2
16.6.3
16.6.4
16.6.5
Operation in Smart Card Interface Mode.......................................................................... 662
16.7.1
16.7.2
16.7.3
16.7.4
16.7.5
16.7.6
16.7.7
16.7.8
Interrupt Sources............................................................................................................... 673
16.8.1
16.8.2
Usage Notes ...................................................................................................................... 675
16.9.1
16.9.2
16.9.3
16.9.4
16.9.5
16.9.6
16.9.7
Receive Data Sampling Timing and Reception Margin in
Asynchronous Mode ......................................................................................... 639
Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode)........................................................................... 660
Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only).................................................................. 675
Data Transfer Format........................................................................................ 638
Clock................................................................................................................. 640
SCI Initialization (Asynchronous Mode) .......................................................... 641
Serial Data Transmission (Asynchronous Mode) ............................................. 642
Serial Data Reception (Asynchronous Mode)................................................... 644
Multiprocessor Serial Data Transmission ......................................................... 650
Multiprocessor Serial Data Reception .............................................................. 651
Clock................................................................................................................. 654
SCI Initialization (Clocked Synchronous Mode) .............................................. 655
Serial Data Transmission (Clocked Synchronous Mode) ................................. 656
Serial Data Reception (Clocked Synchronous Mode)....................................... 658
Sample Connection ........................................................................................... 662
Data Format (Except in Block Transfer Mode) ................................................ 663
Block Transfer Mode ........................................................................................ 664
Receive Data Sampling Timing and Reception Margin.................................... 665
Initialization ...................................................................................................... 666
Data Transmission (Except in Block Transfer Mode) ...................................... 667
Serial Data Reception (Except in Block Transfer Mode).................................. 670
Clock Output Control........................................................................................ 671
Interrupts in Normal Serial Communication Interface Mode ........................... 673
Interrupts in Smart Card Interface Mode .......................................................... 674
Module Stop Function Setting .......................................................................... 675
Break Detection and Processing ....................................................................... 675
Mark State and Break Detection ....................................................................... 675
Relation between Writing to TDR and TDRE Flag .......................................... 676
Restrictions on Using DTC or DMAC.............................................................. 676
SCI Operations during Mode Transitions ......................................................... 677
Rev. 2.00 Sep. 16, 2009 Page xxi of xxviii

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