R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 653

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Note:
Bit
2
1
0
*
Bit Name
TEND
MPB
MPBT
Only 0 can be written, to clear the flag.
Initial
Value
1
0
0
R/W
R
R
R/W
Description
Transmit End
This bit is set to 1 when no error signal is sent from the
receiving side and the next transmit data is ready to be
transferred to TDR.
[Setting conditions]
•
•
[Clearing conditions]
•
•
Multiprocessor Bit
Not used in smart card interface mode.
Multiprocessor Bit Transfer
Write 0 to this bit in smart card interface mode.
When both the TE and ERS bits in SCR are 0
When ERS = 0 and TDRE = 1 after a specified time
passed after completion of 1-byte data transfer. The
set timing depends on the register setting as
follows:
When GM = 0 and BLK = 0, 2.5 etu after
transmission start
When GM = 0 and BLK = 1, 1.5 etu after
transmission start
When GM = 1 and BLK = 0, 1.0 etu after
transmission start
When GM = 1 and BLK = 1, 1.0 etu after
transmission start
When 0 is written to TDRE after reading TDRE = 1
When a TXI interrupt request is issued allowing
DMAC or DTC to write the next data to TDR
Section 16 Serial Communication Interface (SCI)
Rev. 2.00 Sep. 16, 2009 Page 623 of 1036
REJ09B0414-0200