R5F61662N50FPV Renesas Electronics America, R5F61662N50FPV Datasheet - Page 786

• Manufacturer Part Number: R5F61662N50FPV
• Description: MCU 24KB FLASH 384K 144-LQFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8SX/1600r

Specifications of R5F61662N50FPV

• Core Processor: H8SX
• Core Size: 16/32-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, I²C, IrDA, SCI, SmartCard, USB
• Peripherals: DMA, LVD, POR, PWM, WDT
• Number Of I /o: 92
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 40K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b; D/A 2x8b
• Oscillator Type: External
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 144-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 19 ∆Σ A/D Converter
Figure 19.4 shows an example of ∆Σ A/D converter operation (in multi-channel single mode with
channels 0 to 2 selected).
When A/D conversion is performed for two or more channels (multi-channel single mode), the
analog input on each of the selected channels is A/D converted once in sequence from channel 0,
as described below.
1. A/D conversion is started for the selected channels when the ADST bit in DSADCSR is set to
2. When A/D conversion is completed for channel n, the result is transferred to the corresponding
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Channel 0 (ANDS0)
Channel 1 (ANDS1)
Channel 2 (ANDS2)
Channel 3 (ANDS3)
State of operation
State of operation
State of operation
State of operation
Figure 19.3 Example of ∆Σ A/D Converter Operation (Single Mode for One Channel:
1 by software or by the input of a trigger signal selected by the TRGS1 and TRGS0 bits in
DSADCSR. Execution of A/D conversion is in order of rising channel number, so the order of
precedence starts from channel 0.
∆Σ A/D data register (DSADDRn, n = 0 to 5).
DSADDR0
DSADDR1
DSADDR2
DSADDR3
ADIE
ADST
ADF
Note: *
indicates execution of a software instruction.
Idle
Idle
Idle
Idle
Start A/D
conversion
A/D
Set*
Set*
conversion
1
Channel 1)
Clear*
Idle
A/D
Read the result
conversion result
A/D
Set*
conversion
1
2
Read the result
A/D
conversion result
Clear*
Idle
2